2010 Microchip Technology Inc.
DS39774D-page 145
PIC18F85J11 FAMILY
11.8
PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISG and LATG. All pins on PORTG are digital only
and tolerate voltages up to 5.5V.
When operating as I/O, all PORTG pins have Schmitt
Trigger input buffers. Pins, RG1 and RG2, are multi-
plexed with the AUSART module. The RG1 pin is also
configurable for open-drain output when the AUSART
is active. Open-drain configuration is selected by
setting the U2OD control bit (LATG<7>).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
Although the port itself is only five bits wide, the
PORTG<7:5> bits are still implemented to control the
weak pull-ups on the I/O ports associated with PORTD,
PORTE and PORTJ. Clearing these bits enables the
respective port pull-ups. All pull-ups are disabled by
default on all device Resets.
Most of the corresponding TRISG and LATG bits are
implemented as open-drain control bits for CCP1,
CCP2 and SPI (TRISG<7:5>), and the USARTs
(LATG<7:6>). Setting these bits configures the output
pin for the corresponding peripheral for open-drain
operation. LATG<5> is not implemented.
EXAMPLE 11-7:
INITIALIZING PORTG
CLRF
PORTG
; Initialize PORTG by
; clearing output
; data latches
CLRF
LATG
; Alternate method
; to clear output
; data latches
MOVLW
04h
; Value used to
; initialize data
; direction
MOVWF
TRISG
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
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